1. Field of the Invention
The present invention relates to a technique for reducing the gate induce drain leakage (GIDL), and more particularly, to a row decoder with the low gate induce drain leakage current (GIDL) used in the memory apparatus.
2. Description of the Related Art
FIG. 1 schematically shows a circuit diagram of a conventional row decoder used in a memory apparatus. Referring to FIG. 1, the conventional row decoder comprises a CMOS switch circuit and the CMOS switch circuit comprises two transistors 201 and 203. Wherein, the transistor 201 is a PMOS transistor and the transistor 203 is an NMOS transistor. The drain of the transistors 201 and 203 are jointly coupled to a word line WL; the gate of the transistors 201 and 203 are jointly coupled to a selection signal SEL. In addition, a source of the transistor 201 is electrically coupled to a word line driving voltage VWL, a base of the transistor 201 is electrically coupled to a DC bias VPP, and a source of the transistor 203 is electrically coupled to a DC bias VNN and a base of the transistor 203. Wherein, the DC bias VPP is greater than VNN.
Moreover, an NMOS transistor 205 is further disposed in the conventional row decoder. Wherein, a source and a drain of a transistor 205 are electrically coupled to the source and the drain of the transistor 203 respectively, and a base of the transistor 205 is electrically coupled to the source of the transistor 205. Furthermore, a gate of the transistor 205 is electrically coupled to a word line reset signal WLRST.
When the memory apparatus desires to drive the word line WL, the selection signal SEL is pulled down to a low level, so as to turn on the transistor 201 and turn off the transistor 203. Meanwhile, the word line driving voltage VWL is conducted from the source to the drain, and further to the word line WL by the transistor 201. On the contrary, when the word line WL is not selected by the memory apparatus, the selection signal SEL is pulled up to a high level, so as to turn off the transistor 201 and turn on the transistor 203. Meanwhile, the word line WL is turned off.
Theoretically, when the word line WL is turned off, there should be no current on the word line WL. However, it is not true in the real case. Since the deep submicron technique is continuously developed, the size of the MOS component is becoming smaller and smaller. When the word line WL is turned off, the selection signal SEL on the gate of the transistor 201 is in the high level, which causes a leakage current on the drain flowing to the base. This is the so-called “gate induce drain leakage current (GIDL)”. The GIDL may cause the incomplete turn off of the word line WL, which results in the operation errors.
In order to resolve the GIDL problem, U.S. Pat. No. 6,512,705 disclosed by Jeff Koelling et al. was published in the Micron Technique & Technology in 2003. In the U.S. Pat. No. 6,512,705, a word line driving circuit shown in FIG. 2 was disclosed. In accordance with the technique disclosed in the patent mentioned above, the NMOS transistors 62, 64 and 66 are electrically coupled to the source of the PMOS transistors 46, 48 and 52 respectively, and a local voltage generator is configured to reduce the source voltage of the PMOS transistors 46, 48 and 52, such that the GIDL effect is reduced. The detailed operation should be easily understood by the one of the ordinary skill in the art by referring to the description of the patent.